11Metastability occurs when:AInputs are constantBThe clock is too slowCSetup or hold times are violated, so the output settles unpredictablyDThe power is offView AnswerDiscussWorkspaceReportSaveEasy
13The race-around condition in a JK flip-flop occurs when:AJ = K = 1 and the clock pulse is longer than the propagation delayBJ = K = 0CThe clock is offDOnly J = 1View AnswerDiscussWorkspaceReportSaveEasy
14A T flip-flop with T = 1 will:AAlways holdBToggle on each clock edgeCResetDSetView AnswerDiscussWorkspaceReportSaveEasy
15In an SR flip-flop, the input condition S = 1, R = 1 is:ANo changeBSetCResetDInvalid (forbidden)View AnswerDiscussWorkspaceReportSaveEasy